Laxmipriya Y

VLSI Physical Design Engineer with hands-on expertise in end-to-end ASIC design flow from RTL to GDSII. Proficient in floorplanning, power planning, placement, Clock Tree Synthesis (CTS), routing, and timing closure. Strong command of Static Timing Analysis (STA), setup/hold analysis, RC extraction, and physical verification (DRC/LVS).

Experienced with Synopsys tools — Design Compiler, ICC2, and PrimeTime — across multiple chip-level projects ranging from 6K to 26K standard cells. For achieving clean tape-out signoff.

Physical Design Training at ChipEdge Technologies (2025-01 – 2026-12)

• Completed intensive hands-on training covering end-to-end ASIC physical design using Synopsys tools (Design Compiler, ICC2, PrimeTime).
• Executed multiple chip-level projects covering floorplanning through tape-out signoff.

VLSI Internship (2024-01 – 2024-12)

• Gained practical exposure to VLSI design methodologies and EDA tool flows.

Bachelor of Technology in Electronics & Communication Engineering – Guru Nanak Institutions Technical Campus (2021-01 – 2025-12)

Intermediate (Class XII) (2019-01 – 2021-12)

SSC (Class X) (2019-01 – 2019-12)