M. Tech in EVLSI@ Netaji Subhas University of Technology
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I have completed my B. Tech from KIET Group of Institutions in 2024 primarily focused in Electronics and Communcaition Engineering. Currently pursuing Master of Technology in Embedded Systems and VLSI from Netaji Subhas University of Technology. My area of interest lies in Digital and RTL Design
Qualcomm - Hardware Design Intern (07/2026 - present)
VSDSquadron FPGA Mini Intern at VLSI System Design (05/2026 – 06/2026)
→ SPI Master IP (Mode 0, memory-mapped, state machine driven)
→ GPIO Control IP with direction register
→ Simple GPIO Output IP
→ Full SoC integration with address decoding
→ Simulation validation + hardware validation on VSDSquadron FPGA board
→ Tools used: Open Source
VSDSquadron RISC-V Intern at VLSI System Design (04/2024 – 05/2024)
→ Decoded all six RISC-V instruction formats (R, I, S, B, U, J-type) and generated exact 32-bit binary encodings for 15+ assembly instructions, building hands-on understanding of ISA design and processor architecture
→ Designed and deployed a Full Adder on a RISC-V SoC (VSDSquadron Mini) by configuring GPIO pins in Embedded C and validating all logic combinations using push buttons and LEDs
Digital Logic Design Trainee at Pine Training Academy CoE, KIET (01/2022 – 08/2023)
→ Designed a schematic of a 4-bit signed calculator using Xilinx ISE and performed a simulation
→ Designed Combinational and Sequential Circuits using Schematic and implemented on Nexys Artix 7 FPGA Board
Master of Technology in Embedded Systems and VLSI – Netaji Subhas University of Technology (07/2025 – 07/2027)
Bachelor of Technology in Electronics and Communication Engineering – KIET Group of Institutions (11/2020 – 07/2024)
