Mahesh Pulipalupula

Analog Layout trainee with hands-on experience in IC layout design using Cadence Virtuoso, Synopsys Custom Designer, and Mentor Graphics Design Architect. Skilled in schematic-to-layout conversion, placement, routing, DRC/LVS verification, and layout optimization for parasitic reduction and performance matching in accordance with foundry PDKs. Strong technical foundation combined with good communication and collaboration skills, seeking to contribute to high-performance analog and mixed-signal semiconductor designs.

Analog Layout Trainee - Sumedha IT - Hyderabad, India

(2025-01)

• Assisted in the design and layout of analog and mixed-signal circuits using industry-standard EDA tools.
• Worked on schematic-to-layout conversion, including placement, routing, and DRC/LVS verification.
• Gained hands-on experience with Cadence Virtuoso for full-custom IC layout design.
• Optimized layouts for device matching, parasitic reduction, and performance improvement in accordance with foundry PDKs.
• Collaborated closely with design engineers to ensure layouts met electrical and process requirements.

Bachelor of Technology (B.Tech) - Electronics and Communication Engineering - Nalla Malla Reddy Engineering College (2021-12 - 2025-02)

Intermediate (MPC) - SR Junior College (2019-01 - 2021-03)