RTL Design and Verification Intern
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During this period, gained expertise in RTL design and verification using Python, Linux, SystemVerilog, and Verilog. Mastered Verilog fundamentals and testbench design for validation, and developed proficiency in SystemVerilog for advanced verification tasks.
RTL Design and Verification Intern at SOCDV (2024 – 2024)
During this period, gained expertise in RTL design and verification using Python, Linux, SystemVerilog, and Verilog. Mastered Verilog fundamentals and testbench design for validation, and developed proficiency in SystemVerilog for advanced verification tasks.
Semiconductor IC Design and Testing Program (2024 – 2024)
This program provided me with exposure to the physical design workflow of semiconductor ICs, using industry-standard tools such as TCAD, Cadence, and other EDA software.
Physical Design Intern at VLSI EXPERT (2025 – Present)
During this period, acquired hands-on experience in the complete backend flow including floorplanning, placement, CTS, routing, and signoff processes such as DRC, LVS, and timing closure. Gained exposure to industry-standard EDA tools while working on real-world physical design challenges. Focused on optimizing key design metrics like performance, power, and area (PPA).
B.E in ECE – Sri Eshwar College of Engineering (2022 – 2026)
HSC – Sri Ramana Vidyalaya Montessori Hr Sec School (2020 – 2022)
SSLC – Nadar Higher Secondary School (2019 – 2020)
