RTL Design Engineer (Fresher)
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RTL Design Engineer (Fresher) specializing in Verilog HDL-based RTL development, FPGA prototyping, and functional verification. Hands-on experience designing and verifying UART, SPI, and I²C communication systems with CDC, FSM-based datapaths, and Asynchronous FIFO architectures on Artix-7 FPGA using Xilinx Vivado. Targeting RTL Design and Digital Design Engineer internship and fresher roles in VLSI and semiconductor design.
B.Tech - Electronics & Communication Engineering - Institute of Engineering & Management (IEM), Kolkata (2028)
