Aspiring Physical Design Engineer
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Aspiring Physical Design Engineer with strong fundamentals in Digital Electronics and VLSI Design. Hands-on experience in ASIC RTL-to-GDSII flow using Synopsys ICC2 and PrimeTime, and exposure to Cadence Innovus. Skilled in Floor Planning, Placement, CTS, Routing, and Timing Closure across MMMC scenarios.
Strong understanding of STA, DRC/LVS, and low-power design techniques. Passionate about optimizing PPA and contributing to high-performance ASIC design. Eager to contribute and learn in real-world silicon development projects.
VLSI Physical Design Training in VLSI Physical Design – VLSI Guru Institute (2025-06 – 2026-05)
B. Tech in Electronics and Communication Engineering – Sri Vasavi Institute of Engineering and Technology (JNTUK) (2021 – 2025)
Intermediate – Narayana Junior College (2019 – 2021)
SSC – Narayana (E.M) High School (2018 – 2019)
