Niveditha Kasireddy

Aspiring Design Verification Engineer with hands-on experience in SystemVerilog, UVM, and Verilog, specializing in functional and coverage-driven verification. Experienced in AMBA protocol verification and constrained-random testbench development, achieving 90%+ functional coverage. Strong understanding of UVM architecture, assertions, debugging, and scalable verification methodologies. Seeking to contribute in complex semiconductor projects.

Verification Intern- Maven Silicon - Maven Silicon

(2025-09)

Projects: AXI-VIP – Verification

• Developed a UVM-based VIP for AXI3, verifying multi-channel bus transactions and protocol compliance.
• Built reusable UVM components (Agent, Driver, Monitor, Sequencer, Scoreboard) and designed constrained-random sequences for burst transfers (FIXED, INCR, WRAP).
• Performed waveform debugging and protocol violation analysis using QuestaSim and VCS, achieving 90%+ functional coverage and identifying corner-case issues.

Bachelor of Technology - Electronics & Communication Engineering - Gates Institute of Technology (2020-07 - 2024-05)

Board of Intermediate Education - MPC - Sri Sai Jr college (2018 - 2020)

Board of Secondary Education - SSC - Christ the King high school (2018)

Training - Advanced VLSI Design & Verification - Maven Silicon (2024-09 - 2025-05)