Parth Jaju

Hardware Acceleration Intern at CDAC Chennai (2025-05 – 2025-07)

• Research focus: FPGA-based hardware acceleration techniques for Online Transaction Processing (OLTP) workloads.

Sense-Lab Student Researcher at Prof. Sougata Sen BITS Goa (2025-10 – Present)

• Designed the mechanical enclosure and electronic circuitry for Project Visio, a low-power wearable smart glass engineered for motion tracking and activity analysis.
• Collaborated on Project Hot-Hands, a first-person sign language recognition system; responsible for hardware prototyping and sensor integration to support the machine learning model.

Bachelor of Engineering in Mechanical and Minor in Robotics – Birla Institute of Technology and Science, Pilani (2023-08 – 2027-05)