Parth Patel

M.Tech VLSI student with hands-on experience in RTL design, functional verification, and FPGA prototyping. Skilled in Verilog, SystemVerilog, and UVM with project work spanning AMBA protocol design, DFT, clock domain crossing, and hardware acceleration.

Sofcon India Pvt Ltd Jan 2024 – April 2024

Intern-Machine Learning Ahmedabad, Gujarat

• Built text-classification pipeline; learned Python scripting and dataset handling (useful for hardware verification automation).

Dhirubhai Ambani University September 2024 – Jun 2025

Teaching Assistant Gandhinagar, Gujarat

• Assisted in teaching undergraduate course: Digital Design , Basic Electronics , DSP-Hardware

Dhirubhai Ambani University Jun 2025 – July 2025

Robotics Lab Intern Gandhinagar, Gujarat

• Hands’on with different robotic arms and developed various processor on Fpga that performs forward and backward

6dof work

Master of Technology, VLSI and Embedded Systems June 2024 - June 2026

Dhirubhai Ambani University (DA-IICT), Gandhinagar. CGPA: 8.29

Bachelor of Technology, Electronics and Communication Engineering June 2020 - June 2024

Vishwakarma Government Engineering College (GTU), Gandhinagar. CGPA: 7.59