Pavan V S

Electronics and Communication Engineering graduate working as a Design Verification Engineer, with hands-on experience in SystemVerilog-based functional verification, coverage-driven and assertion-based verification, and Verification IP (VIP) development. Strong foundation in digital design and VLSI, seeking to grow and contribute in a challenging VLSI design and verification role.

Design Verification Engineer at Elobchip Electronics India Pvt Ltd (2026-06 – Present)

• Perform functional verification of digital design blocks using SystemVerilog and UVM-based testbenches.
• Build coverage-driven verification environments, developing functional coverage models to measure and close verification goals.
• Contribute to Verification IP (VIP) development, creating reusable, protocol-compliant verification components.

Design Verification Intern at Elobchip Electronics India Pvt Ltd (2026-01 – 2026-05)

• Built SystemVerilog/UVM testbenches and supported VIP development and protocol verification, gaining hands-on exposure to coverage- and assertion-based verification flows.

B.E. in Electronics & Communication Engineering – PES College of Engineering, Mandya (2026)

Pre-University (PUC) – BGS SC PU College, Hassan District (2022)

SSLC – Shri Adhichunchanagiri English Medium High School, Hassan District (2020)