Pawan Pandey

Senior Principal Physical Design Engineer with 12+ years of experience delivering end-to-end RTL-to-GDSII implementation for high-performance Testchip TOP, SoC and DDR5/LPDDR5/GDDR PHY designs. Expertise spans floorplanning, power planning, placement, CTS, routing, MMMC timing closure, physical verification, EMIR, low-power implementation and signoff. Experienced in customer-facing technical leadership, mentoring engineers and AI-assisted automation using TCL/Python.

Senior Principal Design Engineer at Cadence Design Systems (2022-01 – Present)

• Technical owner for complete Netlist-to-GDSII implementation of Testchip TOP and DDR5/LPDDR5/GDDR PHY designs.
• Led floorplanning, power planning, placement, CTS, routing, Min pulse width, Si-Pi, timing & DDR skew closure, physical verification and signoff.
• Implemented high gate-count (~1–2M gate) designs across advanced technology nodes.
• Designed multi-tap clock trees and H-tree based clock distribution for robust clock delivery.
• Performed clock architecture and clock quality analysis using Cadence implementation and timing tools.
• Closed timing across MMMC scenarios including functional, scan and low-power modes.
• Implemented generated clocks, clock dividers and multiple clock-domain strategies.
• Executed complete PV closure including DRC, LVS, Antenna, Density, PERC and signoff verification.
• Performed Conformal Low Power verification for UPF-based low-power intent.
• Implemented power-gated GDDR designs and validated low-power implementation.
• Led EMIR and power integrity closure using Voltus.
• Interacted directly with customers on implementation strategy, milestones, design reviews, debug and tape-out readiness.
• Mentored five direct reportees and other engineers on timing closure and physical design methodology.
• Developed TCL, Python and AI-assisted automation to improve implementation productivity.

Senior Engineer – Physical Design at Seagate Technology (2019-09 – 2021-12)

• Delivered hierarchical processor and storage SoC blocks from RTL-to-GDSII across multiple tape-outs.
• Owned synthesis, floorplanning, placement, CTS, routing and STA closure.
• Performed IO planning, bump planning and RDL implementation for advanced-node SoCs.
• Closed timing across hierarchical partitions and MMMC scenarios.
• Collaborated with RTL, STA, DFT, package and signoff teams to achieve implementation convergence.
• Developed automation for IO timing budgeting, EMIR waiver handling and implementation flow improvements.
• Resolved congestion, timing and routing issues through iterative physical optimization.
• Supported final signoff and ECO implementation before tape-out.

ASIC Physical Design Engineer II at Synopsys (2016-11 – 2019-08)

• Implemented Netlist-to-GDSII flow for high-speed DDR PHY IPs.
• Performed floorplanning, placement, CTS, routing and physical optimization.
• Achieved timing closure for high-frequency DDR interfaces across multiple scenarios.
• Worked closely with STA teams to resolve setup, hold and clock-related issues.
• Supported physical verification, ECO implementation and signoff convergence.
• Supported EMIR analysis using RedHawk during signoff activities.

IC Design Engineer at Broadcom (2014-02 – 2016-10)

• Worked on backend physical design activities supporting standard-cell and SRAM development.
• Performed floorplanning, placement, routing, timing analysis and physical verification.
• Supported DRC/LVS closure using Calibre.
• Worked with library development teams to understand physical architecture and implementation constraints.
• Automated backend tasks using SKILL scripting.

PG Diploma – CDAC

BE in Electronics Engineering – University of Mumbai