Prathyusha G

Design Verification Engineer with 6+ years of experience in SoC and IP-level verification. Skilled in SystemVerilog, UVM, RAL, xprop, coverage closure, assertion coding, functional and power-aware verification, co-simulation, emulation, and regression management.

Design Verification Engineer at Taltech (2025-02 – Present)

AMD Xilinx – ABASIN UCIe

• Integrated the RAL model and developed RAL testcases.
• Set up UPF, xprop, and Verissimo testbench lint checks and resolved all related issues.
• Merged and analyzed coverage.
• Managed weekly shadow and live UCIe regressions.
• Debugged and fixed register, UPF, and xprop test failures.
• Resolved regression infrastructure-related issues.

Verification Engineer at Mobiveil (2021-09 – 2024-12)

Verification Engineer - AMD Xilinx – UCIe APHY IP at Mobiveil (2021-09 – 2024-12)

• Explored and added VCS compile-time and runtime options in the AMD DJ flow.
• Integrated the RAL model and developed register testcases.
• Enabled UPF, xprop, co-simulation, and emulation setups.
• Updated existing testbench files and added new tests and checkers to support simulation, emulation, and co-simulation environments.
• Executed relevant regressions and analyzed failures.
• Developed functional coverage, merged and analyzed coverage, and improved overall coverage metrics.

Verification Engineer - Cadence – USB 3.1 at Mobiveil (2021-09 – 2024-12)

• Developed and debugged U1, U2, and U3 low-power scenarios.
• Created demo FMEDA flows and implemented the complete FMEDA flow for USB 3.1.
• Wrote assertions and functional coverage for the ASF module.
• Ran regressions for USB 3.1 and ASF modules, analyzed failures, and improved coverage.

DV Engineer / Product Engineer at Harman Connected Services / Chipsolve Technologies Pvt. Ltd. (2017-11 – 2019-08)

DV Engineer at Harman Connected Services (2019-02 – 2019-08)

• Verified SPI and PWM modules for Mobile SoC.
• Developed functional and power-aware testcases.
• Set up xprop and executed both functional and power-aware regressions.
• Debugged regression failures and improved test stability.

Product Engineer at Chipsolve Technologies Pvt. Ltd. (2017-11 – 2019-02)

• Verified AHB slave design functionality.
• Developed an AHB Master UVC.
• Created testcases, functional coverage, and assertions.
• Analyzed coverage and debugged simulation failures.

M.Tech in VLSI Systems Design – BVRIT (2018)