Raghu Rag

DFT Engineer experience in Scan, MBIST, ATPG, LBIST and Tessent-based DFT flow for complex SoCs. Experienced in scan insertion, ATPG pattern generation, DRC debugging, coverage improvement, STIL validation and post-DFT verification. Additional exposure to RTL design, Synthesis, STA and SoC verification.

Design Engineer - VLSI at Bigendian Semiconductors Pvt.Ltd (2024-11 – Present)

Total exp - 2.7 years. Tool - Tessent

• Memory generation and MBIST insertion and validation for RAM's and ROM's
• Scan insertion for ips - NPU, ISP, Ethernet, MIPI, EMMC, SD, digital core etc.
• Posses insertion & architectural knowledge of EDT, OCC, IJTAG, Wrapper chains
• Analyzed & Fixed the DRC violation encountered during scan, mbist insertion and ATPG, -S1, S2, T2, T3, A6, E5 etc
• Pattern generation for mbist, scan chain, stuck @ scan serial, stuck @ scan parallel, tdf
• LBIST, ATPG trace validation - primarily fixed the T24 DRC violation by modifying the scandef
• ATPG coverage improvement, Improvized fault coverage by 9.67 % for ISP block and significant 6~7% for other blocks
• Coverage improvements done via X bounding analyses, test point insertions, analyzing the non scan cell instances, meticulous smoothening of constraints etc
• Zero delay and sdf simulation of mbist and atpg validation
• Validated the hard ip BIST and ATPG via stil files
• Supported RTL and PD team for DFT STA fixes, DFT pinmuxing, trace, ECO's
• Supported ATE teams for stil file generation, debugging, pattern masking
• Worked on automation and AI inclusion in the flow, coverage prediction ML model pre-ATPG
• Apart from DFT, designed bandwidth and latency validation via the NICS and the DDR port with respective ips
• Synthesized and Fixed timing for USB, MIPI, Ethernet at SOC level. SDC creation and validation
• Verified DMA330 & Ethernet Subsystem in SOC architecture, system level Full chip test case of all ips in SOC and GLS

Junior Engineer at TATA Electronics Systems & Solutions (2024-01 – 2024-11)

Asa FATP TestEngineer, responsible for the software testing and troubleshooting of product in the Final Assembly, Testing, and Packaging (FATP) process & ensure the integrity and functionality of software in the device.

Project Contributor at Vasu-A surveillance SOC (2023-08 – 2024-01)

As a part of professional experience, worked on a surveillance SoC from architectural design to validation. Contributed across IP stages in the VLSI flow and collaborated with physical design and ATE teams. Was a part MPW shuttle of the project.

B.Tech in Electronics & Communication Engineering – PES University (2020 – 2024)

Minor Degree in Computer Science Engineering – PES University (2022 – 2023)

12th Board – SGPTA PU College (2018 – 2020)

10th Board – Green Wood High School (2009 – 2018)