Rahul Bhadane

Aspiring Electronics Telecommunication engineer with a strong academic base in embedded systems, circuit design, and programming, seeking an internship in Industrial IoT and Embedded Systems. Driven to apply technical skills in Python, C/C++, Linux, and industrial protocols to contribute to IIoT device integration, system troubleshooting, and edge AI development.

Intern at Vidyalankar Institute of Technology (2024-12 – Present)

• Developed FPGA-based digital systems in the VLSI domain using Xilinx Vivado, focusing on RTL design and verification in Verilog HDL.
• Designed and implemented an 8-bit Arithmetic Logic Unit (ALU), verified through simulation, synthesis, and FPGA implementation.

B.Tech in Electronics and Telecommunication Engineering – Vidyalankar Institute of Technology, Mumbai (2023 – 2027)

XII – Shri Nanasaheb Zulal Bhilajirao Patil Higher Secondary School (2022 – 2023)

X – North Point School, Dhule (2020 – 2021)