Roopesh Acharya

M.E. student in VLSI Design with strong foundations in Verilog/SystemVerilog and CMOS fundamentals. Experienced in Analog Design, Physical Design, and Design-for-Testability (DFT) methodologies with hands-on proficiency in Cadence Genus, Modus, Innovus, and Virtuoso. Delivered projects spanning low-power VLSI techniques, full RTL-to-GDSII flows, scan chain insertion, and sensor interface circuit design.

Actively seeking opportunities in Analog Design, Physical Design, DFT, Layout and Design Verification.

Intern at Alar Innovations (2025-02 – Present)

• Designed and simulated a Smart Traffic Control System using SUMO to analyze traffic flow, congestion patterns, and signal timing optimization.
• Built real-world urban traffic network models by extracting and integrating OpenStreetMap (OSM) data with SUMO for performance evaluation.

Electronics Intern at Karnataka Agencies Mahindra (2023-10 – 2023-12)

• Conducted testing of automotive electronic systems to verify reliability and compliance with quality standards.

Master of Engineering in VLSI Design – Manipal School of Information Science (MAHE) (2025 – 2027)

Bachelor of Engineering in Electronics & Communication Engineering – Mangalore Institute of Technology & Engineering (2021 – 2025)