Ruddarraju Mounika

Motivated and detail-oriented Analog Layout Engineer with hands-on experience in VLSI physical design. Seeking to contribute to high-quality IC layout development while enhancing skills in advanced node technologies and design optimization.

Worked on analog and mixed-signal layout design using Cadence Virtuoso

Analog Layout Engineer

Trained as analog layout engineer in Takshila for 6 months and as 6 months as intern.

Capgemini | 6 Nov 2025 – 5 May 2026

• Worked on analog and mixed-signal layout design using Cadence Virtuoso (45nm technology)
• Designed layouts for current mirrors, differential pairs, and NAND gates
• Ensured DRC and LVS clean layouts
• Applied matching techniques like common centroid and interdigitation
• Worked on routing, via placement, and layout optimization
• Debugged layout issues such as nwell spacing and connectivity error

10th sadhana school with 86 percentage

Intermediate in Narayana junior college with 90 percentage

B.tech in electrical and electronics engineering with cgpa 8.45