Design Verification Engineer
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Results-driven RTL Design and Verification Engineer with extensive hands-on experience in Verilog, SystemVerilog, and UVM-based verification. Proficient in assertion-based verification and functional coverage, dedicated to delivering high-quality verification of digital designs. Committed to leveraging industry-standard methodologies and tools to enhance design integrity and performance. Passionate about driving innovation and excellence in complex digital systems.
Graduate Trainee Engineer at RV-VLSI Design Center (2025-07 – Present)
Engaged in RTL design and verification projects focusing on protocol verification and UVM testbench development.
Advance Diploma in ASIC Design: RTL Design And Verification – RV-VLSI Design Center (2026-01)
B.Tech in Electronics and Communication Engineering – Bharath Institute of Higher Education And Research (2025-04)
