Sakshi Galle

Motivated Electronics and Communication Engineering student with a strong interest in VLSI Design, Digital Electronics, FPGA Development, and Embedded Systems. Hands-on exposure to HDL coding concepts, RTL design, digital circuit implementation, and FPGA-based systems through coursework, certifications, and workshops. Familiar with industry-standard EDA tools and VLSI design flow.

Seeking a VLSI Internship to apply technical knowledge and gain practical experience in semiconductor and chip design technologies.

VLSI Design Trainee at Internshala Trainings (2025-02 – 2025-04)

• Completed an 8-week VLSI Design training program covering HDL coding concepts and digital circuit design.
• Studied combinational and sequential circuits, FSM design, and FPGA implementation concepts.
• Gained exposure to RTL design methodology and VLSI design fundamentals.
• Successfully completed a project and assessments as part of the certification.

Bachelor of Engineering in Electronics & Communication Engineering – Jain College of Engineering, VTU (2023 – 2027)

Pre-University – Raja Lakhamagouda Science PU College (2021 – 2023)