Sandeep Gupta

Physical Design Engineer with 3.9+ years of experience in RTL-to-GDSII implementation across advanced technology nodes (5nm–2nm). Skilled in block-level physical design using Fusion Compiler and ICC2, including floorplanning, placement, CTS, routing, STA, timing closure, ECO, and signoff verification (Physical verification). Experienced in PPA optimization, lowpower implementation (UPF), multi-voltage design, tech file development and validation, and TCL scripting and flow automation.

Contributed to successful tape-outs for advanced-node designs with strong focus on design quality, scalability, implementation convergence, and customer-driven targets.

Sr. R&D Engineer - Synopsys India Pvt. Ltd.

(2022-08)

Executed RTL-to-GDSII block-level implementation, tech file development and validation, and flow development across advance technology nodes, ensuring optimized PPA, robust design quality, timing closure, signoff closure, and successful tape-outs.

• Led tf development and validation, ensuring accurate physical DRC compliance and seamless design flow integration
• Led PPA optimization for 2nm node designs, enabling successful tape-out with ~6% utilization reduction and 5% dynamic power savings.
• Improve Fmax and Power by optimizing clock NDRs and Routing layers constraints and buffer placement strategies.
• Setup and utilized DSO.ai for automated the design exploration achieving optimal PPA.
• Executed RTL-to-GDSII block-level implementation across advanced technology nodes, ensuring timing, power, area, and signoff closure targets.
• Managed hierarchical design comprising multiple instantiated blocks, 1M instances and 36 macros operating at 2.4GHz.
• Optimized physical design flows for non MV and Multi-voltage design (Ensured power grid connectivity, placement of voltage areas and power switch insertion) improving scalability and design convergence
• Resolved critical DRC,ICV DRC, LVS, and congestion issues, enhancing routability and overall signoff quality
• Improved flow efficiency through TCL-based scripting for automation, reducing manual effort and execution time
• Executed timing closure for IP designs using STA, constraint validation, ECO implementation ensuring signoff compliance
• Delivered consistent results by meeting PPA targets, validation milestones, and implementation goals

Physical Design Engineer Intern - AMD

(2021-11 - 2022-07)

Performed floor planning, placement, CTS, routing, and DRC resolution for 5nm test chip improving design convergence and quality.

M.Tech. - VLSI Design & Embedded System - Delhi Technological University (2020-01 - 2022-01)

B.Tech. - Electronics & Communication Engineering - GL Bajaj Institute of Technology and Management (2014-01 - 2018-01)