Sastry Puranapanda
Principal Engineer
Talent
Hyderabad, HyderabadMember since October 9, 2022
Principal EngineerVerilog HDLSystem Verilog HDLUVMSystem CSystem C VerilogVHDLC++Embedded CMicrocontrollers LanguagesPsoCLinuxPerl/tclPythonSynopsys ZOIXSynopsys VCSXilinx ISEModelSimAltera QuartusAldec VerificationCadenceVerdiKeil Micro Vision-IIARMMicrochip PICDSP Code composerMatlabScilabCypress PsoC DesignerDebugger
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Principal EngineerVerilog HDLSystem Verilog HDLUVMSystem C
About
RTL Design and Design Verification
Experience
22 Years Design Verification, RTL ASIC and FPGA SOC
Education
MS Electronics, MTech ECE (PhD)ECE
Skills
Principal Engineer
