M.Tech VLSI Design student with hands-on experience in analog IC design and low-power digital design
M.Tech VLSI Design student at VIT (CGPA: 9.61) with hands-on experience in analog IC design using Cadence Virtuoso (op-amps, LDO regulators, LNAs) and cross-technology SRAM analysis, plus lab exposure to LabVIEW, oscilloscopes, and signal generators for circuit measurement and validation. Also worked on low-power digital design, with two peer-reviewed publications in RTL clock gating and adiabatic logic.
M.Tech - VLSI Design - Vellore Institute of Technology (2025-05 - 2027-05)
BE - Electronics and Telecommunication - Dhole Patil College of Engineering (2021-05 - 2025-05)
