Shalo Dinah

Results-oriented Design Verification Engineer with 3.10 years of experience in SoC/IP functional verification. Specialized in SystemVerilog, UVM, and Assertion-Based Verification (SVA) with a proven record of achieving 100% functional and code coverage closure. Strong expertise in I2C protocol and have good knowledge on APB and AXI protocols, regression debugging, and waveform analysis. Seeking to contribute to high-performance verification teams.

Design Verification Engineer - eInfochips (an Arrow company) - Chennai

(2022-08)

• Extracted features from IP specifications and authored test plans, sequences, and assertions
• Achieved 100% functional and code coverage closure using IMC and VManager
• Automated regression runs and optimized debug turnaround time
• Led debugging of complex timing/protocol violations via waveform analysis and regression reports
• Collaborated with designers to identify RTL issues and drive bug closure on JIRA
• Hands-on experience with I2C protocol and good knowledge on APB & AXI protocols
• Developed SystemVerilog Assertions to enforce protocol integrity and improve coverage
• Delivered VPlan creation and mapping in VManager for structured coverage tracking

B.E. - Electronics & Communication - Holycross Engineering College (2016 - 2020)

M.E. - VLSI Design - College of Engineering Guindy, Anna University (2020 - 2022)