Shruti Patil

I am Analog Layout and Circuit Design Trainee, learning Analog Layout and Circuit Design with hands-on exposure to CMOS layout, LVS/DRC verification, and schematic-to-layout flow using Cadence Virtuoso. I'm passionate about VLSI design and aim to grow into a skilled Analog Layout & Circuit Engineer through continuous learning and practical experience

Analog Layout & Circuit Design Trainee - byMerit institute job-oriented VLSI Training Center - 24th Main, Sector 2, HSR Layout, Bengaluru

(2024-01)

Duration: 8 to 9 Month (Present). Course: ANALOG LAYOUT & CIRCUIT DESIGN (AVD).

• Designed transistor-level Analog circuits such as differential amplifiers and current mirrors
• Performed Schematic & Layout simulations to verify circuit performance
• Developed layouts using matching techniques like common-centroid and interdigitated structures
• Performed schematic design and simulations using Cadence Virtuoso
• Ensured design rule compliance (DRC) and layout-versus-schematic (LVS) verification

Secondary School leaving certificate - SSLC - M G JUNIOR COLLEGE TELSANG ATHANI TALUK, BELAGAVI DISTRICT (2018-01 - 2019-01)

Pre University Course - PUC - OXFORD PU COLLEGE, NAGARABETTA MUDDEBIHAL TQ, BIJAPUR DT (2019-01 - 2021-01)

Bachelor of Engineering - Electronics & Communication (E&C) - Rural Engineering College Hulakoti, Visvesvaraya Technological University (2021-01 - 2025-01)