Sowmya R

VLSI/RTL Verification Engineer with 2+ years of industry experience in ASIC design verification using SystemVerilog and UVM. Currently pursuing M.Tech in VLSI (CGPA: 8.6) at Amrita Vishwa Vidyapeetham. Expertise in CDC/Lint analysis, UVM testbench development, waveform debugging, and AMBA protocol verification. Currently contributing to AI SoC front-end design quality checks at Intel India.

Graduate Intern – RTL Design (AI SoC) at Intel India Private Limited (2025-07 – Present)

Worked as part of RTL Design team for AI SOCs.

• Executed Front-end design Quality Checks: Clock Domain Crossing (Enable, Setup Structural Checks) analysis, RTL Lint to identify and resolve design issues early in the flow.
• Basics of UPF and power-aware design concepts.

ASIC Design Verification Engineer at Xeedo Technologies Pvt. Ltd (2022-07 – 2024-01)

• Developed and executed 20+ UVM-based testbenches in SystemVerilog for ASIC blocks delivered to client Defel Technologies.
• Uncovered and documented 40+ RTL bugs through constrained-random stimulus generation, assertion-based verification (SVA), and waveform analysis in ModelSim.
• Verified AMBA APB, AHB, and AXI protocol compliance across 5+ IP modules, ensuring zero protocol violations.

Intern – Networking & Mobile Communication at BSNL (2020-09 – 2020-12)

Completed a 12-week internship covering OSI model, switching, routing, and 4G/5G mobile communication fundamentals.

M.Tech in VLSI – Amrita Vishwa Vidyapeetham, Amritapuri (2024-08 – 2026-07)

B.Tech in Electronics & Communication Engineering – Vignan Institute of Technology (2018-06 – 2022-06)