Suba S
Developer Trainee
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About
Electrical and Electronics Engineering graduate with hands-on experience in Design for Test (DFT), ATPG, scan insertion, and semiconductor testability solutions. Proficient in Cadence Test tools including Modus_Test and Xcelium Simulator. Additional skills in Java, SQL, Python, web technologies, and manual software testing.
Experience
Design for Test (DFT) Trainee at Anora Instrumentation Pvt. Ltd. (AIPL) (2023-02 – 2023-06)
- Performed ATPG stuck-at and transition fault pattern generation for semiconductor chips.
- Executed scan insertion and conducted coverage analysis and transition delay test coverage analysis.
- Worked with Cadence Test tools including Modus_Test (Labs 1–5) and Modus_Diagnostics (Lab 6).
- Ran Xcelium Simulator for waveform analysis using SimVision and GUI analysis in Modus.
- Applied equivalence checks for DFT DRC rules violations.
- Gained in-depth knowledge of chip architecture and semiconductor test methodologies.
Software Development & Testing Trainee at QSPIDER Institute
- Studied core Java including OOP, control flow, methods, and class relationships.
- Completed coursework in Data Structures and Algorithms (DSA), SQL, web technologies (HTML, CSS, JavaScript), manual testing, and Python.
Education
B.Tech in Electrical and Electronics Engineering – SASTRA Deemed University (2019-06 – 2023-06)
Class XII (Higher Secondary) – SRV Matriculation Higher Secondary School (2016-05 – 2018-05)
Class X (Secondary) – Cauvery Matriculation Higher Secondary School (2015 – 2016)
