Subhash Padamata

Formal Verification Engineer with hands-on experience in SystemVerilog Assertions (SVA), Assertion-Based Verification (ABV), Formal Property Verification (FPV), coverage analysis, RTL debugging, and formal convergence. Experienced with Synopsys VC Formal and Cadence JasperGold for block-level verification of complex RTL designs.

Formal Verification Engineer at Meta VLSI Technologies Pvt. Ltd (2025-02 – Present)

Formal Property Verification | SVA | ABV

• Executed end-to-end verification and debugging for complex designs ensuring high-quality RTL for downstream synthesis and power analysis.
• Utilized Python scripts to automate the generation of tool-specific TCL files, streamlining verification setup and reducing manual effort.
• Completed formal verification training through the LUBIS EDA Bootcamp, gaining hands-on experience in SVA, formal property verification, coverage analysis, and counterexample debugging.

Design Verification Intern at Meta VLSI Technologies Pvt. Ltd (2024-06 – 2025-01)

ASIC Verification | SVA | UVM | Functional Coverage

• Built foundations in VLSI design and ASIC verification — digital logic design, RTL coding, and industry-standard verification methodologies — through structured, hands-on labs.
• Developed and applied SystemVerilog Assertions (SVA), including inline and bind-based assertions, to validate timing relationships and sequence compositions.
• Built UVM verification environments using factory methods and stimulus modeling.
• Applied thread synchronization techniques and closed functional coverage using covergroups and cross-coverage.

B.Tech in Electronics and Communication Engineering – Vishnu Institute of Technology (2024)