Veera Guna Sekhar

Railway Signalling Verification and Validation (V&V) Engineer with 3.5 years of experience planning, executing, and documenting V&V activities for safety-critical systems using the V-Model lifecycle. Hands-on experience in system-level functional testing, IFAT bench simulation, hardware-software integration validation, and requirements traceability across Computer-Based Interlocking (CBI), Electronic Interlocking (IXL), KAVACH ATP/TCAS, and CBTC (ATS and ATP) projects. Experienced in developing test procedures, managing defects end-to-end using Mantis BT, and interpreting scheme plans, interface circuits (IFC), and control tables.

Aware of CENELEC EN 50126, EN 50128, and EN 50129 standards and their application in safety-critical railway projects; actively working towards formal Functional Safety Engineer certification (TUV SUD EN 5012X) and open to employer sponsorship. Currently upskilling in VBA scripting to automate repetitive V&V reporting tasks. Trained junior team members and delivered structured V&V outputs aligned with RDSO and CENELEC requirements across multiple Indian Railway zones.

Junior Engineer – Railway Signalling R&D (V&V Focus) at Medha Servo Drives Pvt. Ltd. (MSDPL) (2023-01 – Present)

• Planned and led V&V scope delivery for assigned CBI/IXL and KAVACH projects; prepared V&V Plans, Design Delivery Checklists, and V&V strategies aligned with the V-Model lifecycle.
• Developed test procedures and test scripts for KAVACH ATP and Electronic Interlocking subsystems, aligned with functional requirements and CENELEC EN 50128 guidelines (awareness level).
• Defined verification scope, coverage criteria, and acceptance criteria for CBI/IXL and ATP projects, incorporating ETCS/ERTMS Level 2 design principles.
• Identified and escalated technical and delivery risks to the V&V Manager during review cycles; maintained structured risk and deviation logs across all lifecycle phases.
• Automating repetitive V&V reporting and tracking tasks using Excel; actively upskilling in VBA to build reusable V&V utilities and reduce manual effort.
• Planned and assigned tasks to V&V team members based on project phase and subsystem requirements; trained and guided junior associates.
• Developed and executed signalling test cases for MMRD (Mumbai Monorail) ATS and ATP subsystems; performed system-level functional testing and interface validation in the CBTC bench/lab environment.
• Performed IFAT bench simulation for the MMRD CBTC project as part of the V&V team; executed manual test cases for ATS and ATP subsystems in a simulated integration environment, contributing to the ISA-approved safety case.
• Executed VDU simulation and application logic testing using FSP tools for IXL design correctness verification prior to Indian Railway network deployment.
• Interpreted scheme plans, interface circuits (IFC), and application logic for 40+ IXL stations; validated control tables and I/O logic against design specifications.
• Analyzed test logs and execution results; identified, classified, and reported anomalies through Mantis BT — tracked defects through full review and resolution cycles.
• Verified corrected change requests with targeted regression testing to confirm defect closure and prevent reoccurrence.
• Reviewed system and hardware requirements for clarity, completeness, consistency, and testability across IXL, KAVACH, and CBTC projects.
• Prepared RTM and TTM for the DMRC Main Line (Metro) project establishing full bidirectional traceability from customer SRS to design elements and test cases — formally accepted by the project team.
• Participated in design reviews and technical walkthroughs from a V&V perspective; presented V&V findings and deviation reports in designer review meetings.
• Participated as a V&V team member in ISA coordination for SIL4 documentation review and safety case approval for KAVACH v3.2, KAVACH v4.0, and MMRD CBTC projects.
• Supported FAT/SAT readiness and ISA audit preparation by ensuring correct and approved V&V artifacts were available; contributed to ISA-accepted safety cases for KAVACH and CBTC projects.
• Coordinated with site teams, project management, and RDSO as a V&V team member for design compliance and delivery sign-off activities.
• Trained and guided junior V&V associates on IXL, IFC, and KAVACH/TCAS V&V concepts, improving team capability and delivery consistency.

B.Tech in Electronics and Communications Engineering – Arjun Institute of Science and Technology, JNTUH (2023-10 – 2026-05)

Diploma in Electronics and Communications Engineering – Andhra Polytechnic, SBTET, Kakinada (2020-06 – 2023-05)