Vijayakumar B

VLSI Enthusiast with Hands-on experience in RTL Design, FPGA Development, and Functional Verification using Verilog and SystemVerilog, with hands-on exposure to simulation, synthesis, timing analysis, and digital communication protocols.

Hardware Engineering Intern at Enerzolve Smart Technologies (2026-02 – 2026-05)

• Designed PCB schematics and Learnt Footprint, Layout Basics using Altium Designer and KiCad
• Performed component selection and circuit design for embedded systems
• Collaborated on hardware-firmware integration and debugging, And Hardware Testing
• Contributed to ultrasonic smart water meter and smart energy meter development

Bachelor of Engineering – BMS College of Engineering, Bangalore

Pre-University (PU) – Nalanda PU College, Jagalur

SSLC (10th) – Govt High School Thoranaghatte, Jagalur