VLSI Engineer with M.Tech in VLSI Design
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VLSI Engineer with an M.Tech in VLSI Design and specialized expertise in Analog Layout and Physical Verification. Proficient in the Cadence Virtuoso suite and Mentor Graphics (Siemens) Calibre for executing rigorous DRC/LVS/PEX sign-off across 45nm to 250nm CMOS nodes. Proficient in translating complex schematic intent into high-precision silicon through parasitic-aware routing, LDE mitigation, and optimized floorplanning.
Technically adept in VLSI Physical Design flows, including partitioning and routing, with a proven track record of ensuring signal integrity and area efficiency for first-pass silicon success.
M.Tech in VLSI Engineering – Indian Institute of Information Technology IIITT (2025-01 – 2027-12)
B.E in Electronics and Communication Engineering (Fintech & Blockchain) – Dhirajlal Gandhi College of Technology (2021-01 – 2025-05)
