Vipul Kumar

Owned end-to-end LoRA fine-tuning of a 20B-parameter Qwen-Image-Edit model on 120 distinct author art styles — collecting, cleaning, and structuring per-style datasets, then training across multiple B200 GPUs; achieved 98% cosine similarity (CLIP image-embedding) between generated and reference art, proving faithful per-author style reproduction across all 120 styles. Served a Qwen3.5-9B LLM on RunPod serverless GPUs for NiftyBooks author tools via vLLM (continuous batching + PagedAttention) with speculative decoding, NVFP4 quantization, and custom CUDA/Triton kernels for MCP tool-calling hot paths; lifted serving throughput ~4x, cut VRAM ~4x, and held p99 latency <200ms. Built a Qwen2-VL auto-captioning pipeline exported to a TensorRT engine (FP16, dynamic shapes) to clear large backlogs of un-captioned assets for the authoring tools.

Senior AI Systems & Infrastructure Engineer - NiftyBooks & NiftyIP - Vienna, Austria (Hybrid)

(2025-07)

• Owned end-to-end LoRA fine-tuning of a 20B-parameter Qwen-Image-Edit model on 120 distinct author art styles — collecting, cleaning, and structuring per-style datasets, then training across multiple B200 GPUs; achieved 98% cosine similarity (CLIP image-embedding) between generated and reference art, proving faithful per-author style reproduction across all 120 styles.
• Served a Qwen3.5-9B LLM on RunPod serverless GPUs for NiftyBooks author tools via vLLM (continuous batching + PagedAttention) with speculative decoding, NVFP4 quantization, and custom CUDA/Triton kernels for MCP tool-calling hot paths; lifted serving throughput ~4x, cut VRAM ~4x, and held p99 latency <200ms.
• Built a Qwen2-VL auto-captioning pipeline exported to a TensorRT engine (FP16, dynamic shapes) to clear large backlogs of un-captioned assets for the authoring tools.
• For NiftyIP, built a Google DeepMind SynthID-inspired invisible image watermark embedding robust signals via DCT/DWT mid-band coefficients, trained adversarially against JPEG (QF 10-100), crop (up to 50%), blur, and color jitter; sustained 98.4% bit-retrieval accuracy and <0.6 BER across ~50k test images at PSNR >42 dB, and reframed the verifier as a membership-inference defense (0.82 AUC, 89% precision at 5% FPR) for EU AI Act provenance compliance.

Senior XR, Simulation & Systems Engineer - Hydra eSupport - Pune, India

(2024-06 - 2025-06)

• Architected large-scale spatial simulation and real-time rendering pipelines in Unreal Engine and NVIDIA Cosmos, leveraging GPU instancing, BVH culling, and LOD streaming at ~60 fps to generate 100,000+ validated simulation frames for AV sensor synthetic data infrastructure.
• Optimized spatial simulation rendering for headset-class XR and AV sensor synthetic data pipelines, cutting frame-time from ~22ms to ~11ms and holding sub-20ms motion-to-photon latency; mentored 3 junior engineers on BVH culling, GPU instancing, and clean engine architecture.
• Tuned real-time render pipelines for Meta Quest 3 (Adreno GPU) and Apple Vision Pro via single-pass stereo rendering, OpenXR fixed foveated rendering (FFR), and tile-based deferred-rendering (TBDR) passes that respect mobile-GPU bandwidth limits; cut fragment shading cost ~40%, held 72Hz on Quest 3 and 90Hz on Vision Pro, and avoided thermal throttling on long sessions by gating foveation density against the SoC power budget.

B.Tech - Computer Science and Engineering - Lovely Professional University (2022-08 - 2026-05)

12th Science (CBSE) - Army Public School (2020-04 - 2022-05)