Vishnu Vardhan

ASIC Design Engineer with 2.5+ years of experience in RTL Design, ASIC Development, SoC Integration, FPGA Prototyping, and Digital Design, delivering high-performance and scalable hardware solutions across the semiconductor domain. Strong expertise in SystemVerilog, Verilog, RTL Micro-Architecture, Functional Verification, AXI4, AXI4-Lite, AHB, APB, Memory Subsystems, and Clock Gating, with hands-on experience in developing robust and synthesizable digital designs. Proficient in industry-standard EDA tools including Synopsys VCS, Verdi, SpyGlass, Design Compiler, Formality, Vivado, Github and Linux, with a proven ability to debug complex RTL issues, automate design workflows, and optimize design quality.

Highly collaborative engineering professional with strong analytical and problem-solving abilities, experienced in cross-functional design and verification environments, committed to delivering high-quality ASIC solutions while continuously enhancing expertise in advanced VLSI and verification methodologies.

ASIC Design Engineer at Architect Silicon Inc. (2026-01 – Present)

• Design and develop synthesizable RTL for FPGA-to-ASIC data transfer solutions.
• Review and optimize AI-generated RTL code to ensure compliance with design standards
• Debug failure problems to identify root causes, and suggest effective design fixes
• Enhance RTL coding methodologies to improve design performance, scalability, and maintainability.

Hardware Developer at ISDL - IBM India Pvt. Ltd. (2024-08 – 2025-12)

• Designed and implemented features like Clock Gating, ID buffering, RV Staging, parity gen-check, scrubbing for high speed memory blocks in AXI4-based SRAM memory subsystems
• Developed high-performance data transfer blocks such as OoO Buffer, Data converter, Par. FIFO, I/F registering with Handshake and Quad-write Ring Buffer.
• Contributed to block development supporting the data transfer in PCIe Unit.
• Collaborated with cross-functional teams to resolve integration, simulation, and functional verification issues.

Hardware Intern at ISDL - IBM India Pvt. Ltd. (2024-01 – 2024-07)

• Developed RTL for AXI4-based on-chip memory subsystem implementation.
• Automated AXI glue logic generation using Python-based scripting solutions.
• Participated in design reviews and contributed to improving RTL quality and verification efficiency

Master of Technology in Microelectronics & VLSI Design – NIT Calicut (2022-08 – 2024-07)

Bachelor of Technology in Electronics & Communication Engineering – RVR & JC College of Engineering (2017-07 – 2021-07)