Yeddula Pavan

Motivated VLSI Physical Design engineer looking to apply my training in physical design and optimization. I aim to contribute to innovative semiconductor projects while learning and growing within a dynamic team, I am eager to use my skills in EDA tools and design principles to help create cutting edge technology. Worked on a block implementation from RTL to GDSII

PHYSICAL DESIGN TRAINED FRESHER - Takshila Institute of VLSI technologies

Completed Physical Design training in Takshila Institute of VISI technologies

BLOCK LEVEL IMPLEMENTATION ENGINEER - Takshila Institute of VLSI technologies

Executed Netlist to GDS flows for one block. Project specifications: 40 macros, 56K standard cell count, 416MHz frequency, 9 metal layers, 32nm technology node, 6 months duration.

• Responsible for handling a block from synthesis to GDS-II file generation
• Contains 40 macros, 56K of standard cell count
• Responsible for creating Floor plan, Power plan and Routing
• Responsible for creating clock network to minimize skew and latency
• Executed Nellist to GDS flows for one block
• Keepout margin is created for all macros to reduce pin density
• Solved legalization issues while performing placement
• Solved congestion problems using congestion map
• Cell density is found after post placement and it resolved
• Constructed the clock network to minimize skew and latency
• Resolved multiple opens & shorts during routing
• Tools used: Synopsys ICC, FC Shell

B.Tech - ECE - Sri Venkatesa Perumal College of Engineering & Technology, Puttur (2024)

Diploma - PVKK 2nd Shift diploma, Anantapur (2021)

10th - Z.P.B.H School, Gorantla (2018)