Zeet Mandhana

Worked on hardware acceleration for image-processing and edge-AI applications, focusing on FPGA-based compute architectures and hardware–software co-design. Designed and verified pipelined image-processing accelerators using Verilog and Vitis HLS, integrating them into an FPGA-based processing system. Developed parallel-core and streaming architectures for hardware acceleration, targeting improved computational throughput and reduced latency in real-time vision workloads.

Research and Development Intern - Centre for Defence Technology Innovations and Strategies (CDTIS), IIT Bombay

(2026-05 - 2026-07)

• Worked on hardware acceleration for image-processing and edge-AI applications, focusing on FPGA-based compute architectures and hardware–software co-design.
• Designed and verified pipelined image-processing accelerators using Verilog and Vitis HLS, integrating them into an FPGA-based processing system.
• Developed parallel-core and streaming architectures for hardware acceleration, targeting improved computational throughput and reduced latency in real-time vision workloads.
• Explored FPGA-based AI acceleration techniques for real-time vision workloads, translating computationally intensive image-processing operations into hardware for improved performance and efficiency.
• Worked with RISC-V-based processing, FPGA interconnects, and on-chip memory architectures, with emphasis on resource-efficient system integration.
• Performed RTL/HLS verification, performance analysis, resource evaluation, and FPGA implementation to validate the proposed architectures.
• Built a software reference implementation for the vision-processing pipeline to support algorithm validation and hardware verification.

Technical Intern - Radiant Corporation, Hyderabad - Hyderabad

(2024-05 - 2024-06)

• Gained practical exposure to defense-grade manufacturing environments, including operations within a Class 100,000 cleanroom facility, adherence to controlled workflow protocols, and precision assembly of electro-optic systems to stringent reliability standards.
• Participated in the live demonstration of a tactical drone system during Indian Army tender trials held at Bakloh, Dalhousie.

B.Tech - Microelectronics and VLSI Engineering - Indian Institute of Technology Mandi (2024 - 2028)

ISC, Class XII - Gitanjali School Hyderabad (2011 - 2023)

ICSE, Class X - Gitanjali School Hyderabad (2011 - 2023)