Physical Design Engineer

Company Description

Tech Mahindra is a global leader in providing technology consulting and digital transformation solutions to enterprises across industries. With a team of over 149,000 professionals across 90+ countries, Tech Mahindra serves more than 1,100 clients globally, delivering services such as IT, business process management, engineering, AI, and cloud solutions. Recognized with the Sustainable Markets Initiative's Terra Carta Seal, the company is committed to a sustainable and innovative future.

As part of the Mahindra Group, founded in 1945, Tech Mahindra is known for its reputation as a trusted multinational organization driving innovation. Visit www.techmahindra.com to learn more and #ScaleAtSpeed.

Role Description

This is a full-time on-site role for a Physical Design Engineer located in the Kochi Metropolitan Area.

The Physical Design

Engineer will be responsible for chip floor planning, placement, clock-tree synthesis (CTS), routing, and timing closure. The role also includes driving performance optimization, checking signal integrity, performing power analysis, and ensuring design rules and chip layout meet performance requirements. Collaboration with cross-functional teams to resolve complex design challenges and to ensure successful project deliveries will be critical.

Qualifications

• Experience in chip floor planning, physical placement, and routing
• Proficiency with clock-tree synthesis (CTS) and timing closure tools
• Knowledge of signal integrity and power analysis methodologies
• Understanding of physical verification processes, such as Design Rule Checking (DRC) and Layout Versus Schematic (LVS)
• Strong problem-solving skills and the ability to address complex physical design challenges
• Familiarity with industry-standard design tools such as Cadence, Synopsys, or Mentor Graphics
• Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, or a related field
• Excellent collaboration and communication skills for cross-functional project coordination
• Prior experience with advanced technology nodes (7nm, 5nm, or below) is preferred