Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape.

Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality.

Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward.

Description

Company Description

Essential Duties And Responsibilities

Drive the development of GDR/EDR for new design concepts, advanced layouts, and emerging process technologies during the first product implementation of a new process generation platform (mother device).

Partner with Design, CMOS, and Process Engineering organizations to define product mask requirements and deliver manufacturing-ready mask data.

Design test element groups (TEGs) and define design rules for next-generation CMOS development, enabling robust evaluation of new device structures, layouts, and process technologies.

Drive improvement of CMOS characteristics toward mass production, including reliability enhancement, variability reduction, performance optimization, and manufacturability improvement.

Evaluate design-process interaction risks at early development stages and establish optimized layout, CMOS design, and process solutions to maximize manufacturability, yield, and product robustness.

Serve as the technical owner for GDR/EDR and CMOS design deliverables, defining technical direction, identifying technology gaps, establishing execution plans, and driving closure of critical issues through product-mask release.

Drive cross-functional alignment among Design, CMOS, Process Integration, Device Engineering, Reliability, Product Engineering, Manufacturing, and joint-development partner organizations.

Lead resolution of complex CMOS design, layout, and process-integration challenges, including design-rule conflicts, device reliability risks, variability, performance limitations, and interactions among layout, device design, and wafer processes, using structured and data-driven root-cause analysis.

Develop and apply advanced methodologies for design-rule validation, TEG characterization, CMOS performance and reliability evaluation, variability analysis, statistical modeling, and automation to accelerate learning and improve development quality.

Act as a key technical interface for global development activities, driving alignment and technical execution across organizations in Japan, international engineering teams, and joint-development partner organizations.

Mentor, coach, and develop engineers in GDR/EDR, CMOS design, device engineering, and design-process integration by providing technical guidance, sharing domain expertise, fostering innovation, and cultivating the next generation of technical leaders.

Qualifications

REQUIRED

Ph.D. or M.S. degree in Electrical Engineering, Applied Physics, Materials Science, or a related field, with typically 10+ years of relevant semiconductor industry experience.

Deep technical expertise in CMOS device design, semiconductor device physics, design-rule development, TEG design and characterization, layout verification, and design-process interaction.

Experience with advanced NAND flash memory technologies is highly desirable.

Demonstrated experience defining or developing GDR/EDR for new process technologies, advanced layouts, or first-product implementation of a new process generation platform.

Demonstrated experience designing TEGs and defining design rules for next-generation CMOS technology development.

Strong understanding of CMOS performance, reliability, variability, device and process interactions, manufacturability, yield-risk assessment, and requirements for mass-production readiness.

Proven track record of leading and influencing complex cross-functional development programs involving Design, CMOS, Process Integration, Device Engineering, Reliability, Product Engineering, and Manufacturing organizations.

Demonstrated ability to identify and resolve highly complex CMOS design, layout, and process-integration challenges and to drive technical alignment across organizations without direct managerial authority.

Experience with design-rule checking, layout analysis, device characterization, reliability evaluation, statistical analysis, computational modeling, and automation tools is highly desirable.

Demonstrated success working within global teams and leading collaborations across multiple geographic regions and joint-development partner organizations.

Strong English communication and presentation skills are required.

While

Japanese proficiency is not required at the time of hire, candidates are expected to actively and independently learn Japanese and aim to achieve effective working-level communication in Japanese within approximately two years.

The individual must be self-motivated and self-directed, with a demonstrated ability to influence, collaborate, make sound technical judgments, and drive outcomes across organizational boundaries.

Additional Information

Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution.

Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at jobs.accommodations@sandisk.com to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying.

会社概要

Sandiskは、人々や企業がどのようにデータを活用しているかを深く理解し、現在のニーズだけでなく、未来の新しいアイデアを実現するソリューションを提供するため、絶えずイノベーションを追求しています。

フラッシュメモリおよび先進メモリ技術における画期的なイノベーションの長い歴史を持ち、私たちのソリューションは、今日のデジタル社会を支える重要な基盤となっています。

Sandiskは、卓越した製造技術と、イノベーション、性能、品質において世界的に評価される業界トップクラスの製品ポートフォリオを強みに、人々や企業のさらなる可能性を支えています。

また、Sandiskの2つの施設は、先進的な第4次産業革命（4IR）イノベーションにより、世界経済フォーラムの「Global Lighthouse Network」に認定されています。さらに、効率的なオペレーションにおける革新的な取り組みにより、「Sustainability Lighthouse」にも認定されています。

グローバルな事業展開を通じて、世界のサプライチェーンに必要なフラッシュメモリを提供し、デジタル社会の発展を支えています。

主な業務内容

新プロセス世代プラットフォームにおける最初の製品適用（Mother Device）に向けて、新しいDesign Concept、先端Layout、新規Process Technologyに対応したGDR/EDRの開発を主導

Design、CMOS、Process Engineering部門と連携し、Product Mask要件を定義するとともに、量産適用可能なMask Dataを作成

次世代CMOS開発に向けたTEG（Test Element Group）の設計およびDesign Ruleの策定を行い、新しいDevice Structure、Layout、Process Technologyを適切に評価できる環境を構築

Reliability向上、Variability低減、Performance最適化、Manufacturability改善など、量産に向けたCMOS特性改善を推進

開発初期段階からDesign-Process Interactionのリスクを評価し、Manufacturability、Yield、Product Robustnessを最大化するためのLayout、CMOS Design、Process Solutionを確立

GDR/EDRおよびCMOS Design DeliverablesのTechnical Ownerとして、技術方針の策定、Technology Gapの特定、実行計画の策定を行い、Product Mask Releaseまでの重要課題の解決を推進

Design、CMOS、Process Integration、Device Engineering、Reliability、Product Engineering、Manufacturing、および共同開発パートナー間のCross-functionalな連携・合意形成を推進

Design RuleのConflict、Device Reliability Risk、Variability、Performance Limitation、Layout・Device Design・Wafer Process間の相互作用など、複雑なCMOS Design、Layout、Process Integration上の課題について、体系的かつデータドリブンなRoot Cause Analysisを用いて解決を主導

Design Rule Validation、TEG Characterization、CMOS性能・信頼性評価、Variability Analysis、Statistical Modeling、Automationなどの高度な評価・解析手法を開発・適用し、開発サイクルを加速するとともに開発品質を向上

Global Developmentにおける主要なTechnical Interfaceとして、日本、海外Engineering Team、共同開発パートナー間の技術的なAlignmentとExecutionを推進

GDR/EDR、CMOS Design、Device Engineering、Design-Process Integration領域のエンジニアに対して、Technical Guidance、専門知識の共有、Innovation促進などを通じてMentoring、Coaching、人材育成を行い、次世代Technical Leaderを育成

応募資格

必須要件

電気・電子工学、応用物理、材料科学、または関連分野の博士号（Ph.D.）または修士号（M.S.）を有し、通常、関連する半導体業界で10年以上の実務経験を有すること

以下の領域における高度な専門知識

CMOS Device Design

Semiconductor Device Physics

Design Rule Development

TEG Design / Characterization

Layout Verification

Design-Process Interaction

先端NAND Flash Memory Technologyの経験があれば非常に望ましい

新しいProcess Technology、Advanced Layout、または新Process Generation PlatformのFirst Productへの適用において、GDR/EDRを定義・開発した実績

次世代CMOS Technology Developmentに向けて、TEGを設計しDesign Ruleを策定した実績

CMOS Performance、Reliability、Variability、Device-Process Interaction、Manufacturability、Yield Risk Assessment、およびMass Production Readinessに関する深い理解

Design、CMOS、Process Integration、Device Engineering、Reliability、Product Engineering、Manufacturingなど、複数部門が関係する複雑なCross-functional Development Programをリードし、影響力を発揮した実績

CMOS Design、Layout、Process Integrationに関する高度かつ複雑な技術課題を特定・解決し、直接的なManagerial Authorityを持たない状況でも、組織横断で技術的なAlignmentを推進できる能力

Design Rule Checking、Layout Analysis、Device Characterization、Reliability Evaluation、Statistical Analysis、Computational Modeling、Automation Toolなどの経験があれば非常に望ましい

Global Teamの一員として業務を遂行し、複数の地域・共同開発パートナーにまたがるCollaborationをリードした実績

高い英語コミュニケーション能力およびプレゼンテーション能力

入社時点で日本語能力は必須ではありませんが、入社後は自主的かつ積極的に日本語を学習し、おおむね2年以内に業務上効果的にコミュニケーションできるレベルを目指すことが期待されます。

高いSelf-motivationとSelf-directionを持ち、組織の枠を越えて他者に影響を与え、協働し、適切な技術判断を行い、成果を実現できること

その他

Sandiskは、多様性が持つ力と可能性を大切にしています。グローバル企業として、お客様や地域社会の多様性を社内にも反映することが重要であると考えています。

さまざまな視点を融合することが、従業員、会社、お客様、そして社会にとって最良の成果につながると考え、一人ひとりが所属意識を持ち、尊重され、それぞれの力を発揮できるインクルーシブな環境づくりに取り組んでいます。

また、Sandiskは、障がいのある応募者にも公平な機会を提供し、すべての候補者が採用サイトおよび採用プロセスを適切に利用できるよう取り組んでいます。採用プロセスにおいて合理的配慮が必要な場合は、必要な配慮の内容、Job Title、およびRequisition Numberを記載のうえ、指定の窓口まで連絡することができます。

Principal Engineer, Technology Development Engineering

職務内容