Dong Nguyen Van
RTL Design Verification
人材
東京都, Tokyo0登録日 2023年4月22日
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紹介
- Digital Design and Verification Engineer for more than five years with experience in design and verification on SoC.
- Experience in Verilog/ System Verilog-based verification, UVM methodology with AMBA bus protocol (APB, AHB, AXI).
- Familiar with some EDA design tools: Synopsys (Vcs, Design Compiler, Verdi); Cadence (xcelium, simvision), FPGA Xilinx Vivado.
経歴
- Digital Design and Verification Engineer for more than five years with experience in design and verification on SoC.
- Experience in Verilog/ System Verilog-based verification, UVM methodology with AMBA bus protocol (APB, AHB, AXI).
- Familiar with some EDA design tools: Synopsys (Vcs, Design Compiler, Verdi); Cadence (xcelium, simvision), FPGA Xilinx Vivado.
学歴
Bachelor's degree in Electronic and Communication Engineering
