DFT/DFX Engineer

KEY RESPONSIBLITIES:

· Collaborate with architects, design engineers, and firmware engineers to understand the new DFT features to be verified.

· Estimate the time required to write the new feature tests and any required changes to the test environment.

· Build the directed and random DFT verification tests.

· Debug test failures to determine the root cause; work with RTL/DFT and firmware engineers to resolve design defects and correct any test issues.

· Analyze and enhance legacy DFT test plans to accommodate new Design for Debug feature developments.

· Recreate post-silicon failures in pre-silicon environment.

· Conduct silicon debug and root cause analysis with minimal logging support.

· Utilize JTAG protocols for debugging and validation.

PREFERRED EXPERIENCE:

· Bachelor's or Master's degree in Electrical/Electronics/Computer Engineering, or a related field.

· 3 - 5 years of experience in DFT Design Verification with strong debug capabilities.

· Experienced with SystemVerilog/UVM testbench development for complex SoCs Including GLS & SDF verifications.

· Hands-on experience with DFT/DFX methodologies, including Scan, ATPG, MBIST, Boundary Scan, or related techniques.

· Advanced scripting skills (Tcl, Python, Perl, etc.) for automation and testbench infrastructure.

· Deep knowledge of digital design, RTL design, and verification flows.

· Strong troubleshooting and analytical debugging skills with ability to debug without logs.

· Ability to quickly adapt to complex infrastructure environments.

· Excellent hands-on debug skills and attention to detail.

· Proficient in debugging firmware and RTL code using simulation tools.

· Emulation execution background is a plus.