Sanjan Kumar

Analog Layout Engineer with hands-on experience in TSMC 28nm and GF12nm FinFET technologies. Skilled in floorplanning, device matching, DRC/LVS, EM/IR analysis, and physical verification. Delivered clean sign-off layouts for Bandgap Reference, LDO, Comparator, and high-speed DAC Clock Tree.

Analog layout Engineer - Omni Design Technologies

(2026-02)

• Designed Standard Cells (Inverter, NAND, DFF, Level Shifter) in TSMC 28nm using Euler Path methodology to minimize area and routing complexity
• Laid out Comparator (Sense Amp + Strong ARM Latch) in GF12nm FinFET, resolving RDRC/DP violations and achieving clean DRC/LVS sign-off
• Delivered Bandgap Reference, LDO Pass Transistor (50 mA), and DAC Clock Tree layouts with Common Centroid matching, sidewall shielding, and EM/IR-validated routing

ASIC Full Custom Layout Trainee - RV – VLSI Design Centre

(2025-07 - 2026-01)

• Designed Standard Cells, Opamp, and 6T SRAM layouts across 28nm, 40nm, and 90nm nodes using Synopsys Custom Compiler and IC Validator
• Performed physical verification including DRC/LVS on all implemented layouts, achieving clean sign-off results
• Built foundational expertise in full-custom layout methodologies and foundry design-rule compliance

Machine Learning Intern - Alar Innovation Limited - Manipal

(2025-02 - 2025-05)

AI-Driven Urban Traffic Optimization & Predictive

• Built an AI Traffic Management System using YOLO v8/v11 and OpenCV, improving signal-flow efficiency by 30%
• Integrated predictive modeling for real-time congestion forecasting and urban mobility planning
• Deployed end-to-end pipeline with SORT tracker and Python, enabling frame-level vehicle detection and classification

Advanced Diploma - Full Custom ASIC Design - RV – VLSI Design Centre (2026)

Bachelor Degree - Electronics and Communication - Mangalore Institute of Technology & Engineering College (2025)

PUC - Shri Mahaveera PU College (2021)

SSLC - Kumbhashree English Medium Highschool (2019)