Vladislav Severin

Motivated Computer Engineering junior at UC Santa Cruz passionate about digital hardware design, computer architecture, and embedded systems. Experienced in structural Verilog HDL, logic synthesis, and open-source ASIC tapeout (Tiny Tapeout / SKY130). Seeking a summer 2026 internship in digital hardware, FPGA development, or embedded systems.

Software Engineering Intern at Vcinity, Inc. (2025-06 – 2025-08)

• Deployed, stress-tested, and optimized Java Spring microservices and data pipelines on Red Hat Linux under high-load, achieving optimal packet loss while preserving performance.
• Wrote automated REST/API tests in Postman and Java that caught multiple defects pre-production.
• Built daily build/test infrastructure with Linux VMs and custom ISOs, shortening QA feedback cycle.

B.S. in Computer Engineering, Digital Hardware Concentration – University of California, Santa Cruz (2027-06)

A.A. in Computer Engineering – West Valley College (2024-05)