Ashok H

Currently working as a Design Verification Engineer at Nationz Innovations Private Limited.

Key skills

• Feasibility study, Micro-architecture and design specification creation for IP.
• RTL designs involving multiple clock domains in Verilog.
• Low power design and simulations
• Lint, CDC Analysis using Spyglass
• Basic knowledge of standby-wakeup, interrupt architecture and overall CPU subsystem of ARM processors.
• Expertise in APB/AHB architecture and serial communication protocols such as SPI, UART, USART, I2C etc.
• Involved into simulation and verification tasks of SOC / IP designs.
• Working with design teams for design function verification & performance evaluation.
• Reusable verification environment development, methodology research & flow setup.
• Supporting design debug , FPGA emulation , lab validation, silicon bring up and mass production.
• Expertise in System Verilog, UVM methodologies and Perl Scripting.

Former Senior Systems Engineer with 2.8 years of experience in the area of Network Design Management, Telcom business (FTTx & HFC), Process Automations, Business Analysis & Branding

Verification of SPI Protocol

The SPI Protocol provides half-duplex,full-duplex and synchronous serial communications with external devices. Some of the features include:

• Master and Slave operation
• Full duplex and half duplex synchronous transfers
• Multi master capability
• Programmable clock polarity and phase
• Programmable baud rate, frame format as well as MSB first or LSB first data ordering
• Various status flags for error and event detection

Verification of RTC module

• RTC provides ultra lower power IP with wake up from low power by interrupts from programmable alarms, tampers, timestamp & wake up timer.
• Features Backup Registers which can be erased on tamper detection.
• Two different clock domains, the APB clock and the RTC clock domain.
• A reference clock which can be used to update calendar
• Daylight saving compensations.

Verification of SMU module

• Chip power up sequences and successfully transitioning into various chip modes.
• Boot up sequences verification & checking for boot from different sources.
• Wake up from chip reset & also from various low power modes.

Currently working on the verification of Memory Management Unit (MMU) & Digital Filter modules.

Wrote UVM Test cases for verification of the IP and estimated the code and functional coverage of the IP as well.

Designed and developed the architecture of I2C/SMBUS IP protocol for an McU SoC. This included:

• I2C Slave Machine, which provides support for address detection as well as STOP detection.
• I2C Master Machine, which provides the clock (Standard Mode & Fast Mode), as well as START and STOP generation.
• Supports various status flags and error flags as well as interrupt vectors.
• Configurable PEC Generation and Verification.
• SMBUS 2.0 compatability.
• DMA capability

Architecture and Implementation of USART/UART IP for an McU SoC

• USART clock module implemented which generates clock for USART Tx and Rx module. Moreover, clock for synchronous mode, prescaled clock for smart card mode was implemented as well.
• USART Tx state machine, which supports data transmission and PEC bit generation as well as support for .5, 1, 1.5 and 2 STOP bits. Furthermore, support for Synchronous mode, SmartCard mode, Hardware Flow Control, DMA as well as support for full duplex and half duplex modes are implemented.
• USART Rx state machine, which supports data reception and PEC error detection as well as support for noise and frame error detection were implemented. Furthermore support for Synchronous mode, SmartCard mode, DMA and full duplex and half duplex are implemented.

Master of Science, Integrated Circuit Design, Joint Degree offered by Nanyang Technological University & Technical University of Munich.

Pursued Masters in the field of Integrated Circuit Design, the focus points being in Digital, Analog as well as Mixed signal circuits. Additionally, has hands on experience on VHDL, Verilog, Matlab as well as Cadence Tools.

Relevant Modules: Digital IC Design, Analog IC Design, Design for Testability, System on Chip Architectures, Digital Signal Processing, Advanced MOSFETS and Novel Devices, IC Packaging, Embedded Systems