CPU Emulation Engineer, Silicon
GoogleJob description
CPU Emulation Engineer, Silicon Share: CPU Emulation Engineer, Silicon
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Locations
- Austin, TX, USA
- Mountain View, CA, USA
- +3 more
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Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.
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Note By applying to this position you will have an opportunity to share your preferred working location from the following:
- Austin, TX, USA
- Mountain View, CA, USA
- Portland, OR, USA
- Poughkeepsie, NY, USA
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 8 years of experience with industry-standard emulation or FPGA prototyping platforms (e.g., Synopsys ZeBu/HAPS, Cadence Palladium/Protium, Siemens Veloce).
- Experience in RTL design using Verilog or SystemVerilog.
- Experience writing scripts or developing automation workflows in Python, Perl, TCL, or Makefiles.
- Experience scaling compilation and routing across multi-FPGA and enterprise emulation platforms.
- Experience verifying and troubleshooting complex semiconductor IP blocks.
- Experience collaborating with cross-functional design verification (DV) and silicon design teams.
- US Salary: $163,000 - $236,000 (USD) + 15% bonus target + equity + benefits
- Learn more about benefits at Google.
- Architect and drive advanced Register-Transfer Level (RTL) partitioning, Field-Programmable Gate Array (FPGA) synthesis, and validation strategies for industry-standard emulation platforms such as Synopsys ZeBu, Cadence Palladium, or Siemens Veloce.
- Define and execute comprehensive test suites, complex performance benchmarks, and software workloads to ensure pre-silicon verification and system-level validation.
- Guide advanced debugging methodologies to rapidly isolate and resolve complex functional failures within multi-million gate subsystem designs and full-chip environments.
- Lead initiatives to optimize model compile times, improve FPGA routing efficiency, and maximize hardware resource utilization across enterprise emulation farms.
- Architect custom automation workflows using modern scripting languages and collaborate with IP design and verification stakeholders to streamline continuous integration.
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