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· Page 1 / 500Overview As one of the world’s leading analytical instrumentation companies, Bruker covers a broad spectrum of advanced solutions in all fields of research and development. All our systems and instruments are designed to improve safety of products, to accelerate time-to-market, and to support indust
TessolveLocation: San Jose | Dallas | Tuscon Summary Tessolve is looking for a Principal ATE Engineer (V93K) to develop and bring up test programs for Digital, PMIC, RF, and Mixed Signal products on both Bench and ATE platforms ( V93K – SmarTest 7/8 ). This role is based out of San Jose, CA or Dallas, TX an
Figure is an AI robotics company developing autonomous general-purpose humanoid robots. The goal of the company is to ship humanoid robots with human level intelligence. Its robots are engineered to perform a variety of tasks in the home and commercial markets. Figure is headquartered in San Jose, C
THE ROLE: In this role, you will be responsible for driving low-power design strategies, synthesis, and timing closure for complex SoC and IP designs. You will use industry-standard EDA tools to optimize power, performance, and area (PPA), ensuring efficient, reliable silicon that meets product requ
About Etched Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference . Backed by hundreds of millions fr
ByteDanceResponsibilities The DataCenter Service / Datacenter Cloud System (DCS) team sits within TikTok's global technology structure and supports the company's fast growth by building and operating hyper-scale datacenters, managing the life cycle of server fleet, providing cloud solutions, and developing v
Samsung SemiconductorPlease Note To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period. Advancing the World’s Technology Together Our technology solutions power the tools you use every day--including smartph
JacobsAt Jacobs, we're challenging today to reinvent tomorrow by solving the world's most critical problems for thriving cities, resilient environments, mission-critical outcomes, operational advancement, scientific discovery and cutting-edge manufacturing, turning abstract ideas into realities that trans
The application window is expected to close on: 11/05/2026 Meet the Team The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and ha
Johnson & Johnson MedTechAt Johnson & Johnson, we believe health is everything. Our strength in healthcare innovation empowers us to build a world where complex diseases are prevented, treated, and cured, where treatments are smarter and less invasive, and solutions are personal. Through our expertise in Innovative Medi
Johnson & Johnson MedTechAt Johnson & Johnson, we believe health is everything. Our strength in healthcare innovation empowers us to build a world where complex diseases are prevented, treated, and cured, where treatments are smarter and less invasive, and solutions are personal. Through our expertise in Innovative Medi
Job Description We are seeking a Staff Foundry Yield Engineer to join our Foundry Yield Engineering team. The position is responsible for driving yield improvement, supporting new product introduction and manufacturing transfers, performing yield and defect data analysis, and providing technical sup
Job Description We are seeking a Staff Foundry Yield Engineer to join our Foundry Yield Engineering team. The position is responsible for driving yield improvement, supporting new product introduction and manufacturing transfers, performing yield and defect data analysis, and providing technical sup
THE ROLE In this role, you will be responsible for driving low-power design strategies, synthesis, and timing closure for complex SoC and IP designs. You will use industry-standard EDA tools to optimize power, performance, and area (PPA), ensuring efficient, reliable silicon that meets product requi
Our client is a global semiconductor leader building high-performance ASICs and SoCs for AI, HPC, data center networking, SerDes connectivity and PCIe switch products. They are looking for a senior Physical Design Engineer to own RTL-to-GDSII implementation at advanced nodes (7nm and below, includin
Job Title: GPU Formal Design Verification Location: San Jose, CA (100% Onsite) Duration : 6 Months Pay Range: $85/hr to $95/hr Job description: Formal Design Verification Engineer, you will be responsible for developing formal constraints, checks, and cover properties to new and existing design bloc
At Johnson & Johnson, we believe health is everything. Our strength in healthcare innovation empowers us to build a world where complex diseases are prevented, treated, and cured, where treatments are smarter and less invasive, and solutions are personal. Through our expertise in Innovative Medi
Samsung SemiconductorPlease Note: To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period. Advancing the World’s Technology Together Our technology solutions power the tools you use every day--including smartp
AIXTRON INCAIXTRON Inc ., serves as our North American sales and service hub. Our team of sales managers, field service and process engineers, and logistics specialists provides customers across North America with high-level technical support, training, and guidance on system operation, maintenance, and optimi
Kratos Defense and Security SolutionsJob Description Kratos Microwave, Inc., a Kratos' company, is looking for a Principal RF Design Engineer 6 to work onsite at either their San Jose, CA facility or their Folsom, CA facility. Kratos Defense & Security Solutions, Inc. (NASDAQ:KTOS) develops and fields transformative, affordable tec
Mirafra TechnologiesKey Responsibilities Develop, review, debug, and verify timing constraints for ASIC designs. Contribute to RTL design and collaborate with design, verification, synthesis, and DFT teams to resolve timing and implementation issues. Analyze timing behavior and support timing closure across functional
Role: Senior RF Test & PCB Design Engineer Location: San Jose, CA Duration: 6+ Months Client: Samsung Semiconductor Job Description: PCB Development: Lead the schematic entry, component selection, and layout routing optimization for complex RF evaluation boards using Cadence Allegro. Simulation
Honeywell AerospaceWe're looking for an experienced and highly skilled Principal RF Design Engineer to join our thriving team in San Jose. In this pivotal role, you will provide leadership and direction in the design and development of advanced RF/Microwave circuits, guiding projects from concept to production. Your d
Astera LabsAstera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integr
Job Title : DFT Engineer Job Location : San Jose, CA and Austin, TX (Onsite) Duration : 12+ Months Job Description: Good understanding of DFT fundamentals and methodology Experience with DFT insertion and verification Experience with Tessent tools: Tessent Streaming Scan Network Op SW Tessent Memory
Job Title : Formal Design Verification Job Location : San Jose, CA (onsite) Duration : 12+ Months Job Description: Formal Design Verification Engineer, you will be responsible for developing formal constraints, checks, and cover properties to new and existing design blocks towards verifying sequenti
Role Overview Cisco’s ASIC Engineering group is seeking a senior RTL / Static Timing Analysis (STA) contractor to support timing constraint development and verification, RTL design, and timing closure across ASIC design flows. The preferred work location is Cisco’s San Jose campus. Candidates with a
JOB DUTIES: In this role, this engineer will be part of a highly technical team that develops test plans, completes functional & electrical validation, & debugs issues for new processor silicon interface features with strong focus on power management. Writes comprehensive electrical & fu
Title: Validation Engineer Location: San Jose, CA Duties: In this role, this engineer will be part of a highly technical team that develops test plans, completes functional & electrical validation, & debugs issues for new processor silicon interface features with strong focus on power manage
