Physical Design Engineer, FullChip/ASIC Implementation

Physical Design Engineer, FullChip/ASIC ImplementationShare Share Physical Design Engineer, FullChip/ASIC Implementation

Location Google Place: Mountain View, CA, USA

Experience Level Mid

Mid Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.

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In-Person Interviews In most instances, this position requires in-person interviews as part of the hiring process.

Minimum Qualifications

• Bachelor's degree in Electrical Engineering or equivalent practical experience.
• 4 years of experience in physical design.
• Experience in one or more synthesis/PnR tools (e.g., Genus, Innovus, DC, ICC).
• Experience in high-performance synthesis, PnR, sign-off convergence, including STA and sign-off optimizations.

Preferred Qualifications

• Experience in top-level floorplanning and block integration.
• Experience in low power design implementation including UPF/CPF, multi-voltage domains, and power gating.
• Experience with ASIC design flows and methodology of physical design.
• Understanding of circuit design, device physics, and deep submicron technology.
• Knowledge of Verilog/SystemVerilog and fundamentals of computer architecture.
• Effective skills with scripting languages such as Tcl, or Perl.

About the Job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US Salary: $138,000 - $197,000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits at Google.

Responsibilities

• Develop all aspects of ASIC RTL2GDS implementation for high Performance, Power, Area (PPA) designs.
• Manage full-chip level physical implementation.
• Define and implement innovative schemes to improve performance and power.
• Work with cross-functional teams to deliver best quality of results.

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Language Proficiency Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

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Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.

Locations Google Place: Mountain View, CA, USA

Experience Level: Mid

Mid Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.