RTL Design Engineer, TPU
GoogleJob description
RTL Design Engineer, TPU Location: Sunnyvale, CA, USA
Experience Level: Mid
Overview: In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU.
You'll contribute to the innovation behind products loved by millions worldwide, leveraging your design and verification expertise to verify complex digital designs, specifically focusing on TPU architecture and its integration within AI/ML-driven systems.
Responsibilities:
- Work separately to create and review management and control subsystem's design microarchitecture specifications.
- Develop SystemVerilog RTL to implement logic for ASIC products according to established coding and quality guidelines.
- Work with architecture and power teams to evaluate features and their impact.
- Collaborate with design validation (DV) teams to create test plans to verify and debug design RTL.
- Work with physical design teams to ensure design meets physical requirements and timing closure.
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- Experience with scripting languages.
- Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with an emphasis on computer architecture.
- 8 years of experience in ASIC design.
- Experience interacting with software, system hardware, and other cross-functional teams.
- Experience with chip management, clocking, reset, and peripherals like I2C, SPI, UART, etc.
- Understanding of digital design fundamentals, including synchronous and asynchronous logic, state machines, and bus protocols.
- US Salary Range: $163,000 - $236,000 (USD) + 15% bonus target + equity + benefits
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Alphabet
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