System Validation Engineer

Position:

System Level Test Engineer

Location:

San Diego, USA

Own design and validation of System Level Test from software perspective.

Develop custom tests on the system level to create the most effective screen tests for SLT

Collaborate with chip design and system validation teams to develop a test plan for System to Tester correlation for optimizing power and performance

Write code to help communicate SLT handler to test controller and to peripherals like temperature control units

Write test methods, scripts and code to create a test Flow encompassing all the key system level tests provided by the systems validation team

Key skill:SLT, HVM, NPI, ATE, Network topology, OSAT , RMA, HTOL, Burn In, bench testing, TPUs, CPUs, GPUs, PCIe, Ethernet , C#, C/C++, PERL, Python, .

NET framework, Security provisioning, Fuse programming

• 3 Years of experience

Experience in Systems Level Test, Systems validation, and/or bench testing.

Experience in day zero bring up of new silicon at the system level

Experience in driving SLT testing in HVM

Experience with testing and characterization of high power Ips like TPUs, CPUs, GPUs in mission mode.

Experience with testing and characterization of High Speed SerDes based IPs (PCIe, Ethernet SerDes etc.)

Knowledge of network topology and experience in network connectivity (HW and SW)

Proficient in C#, C/C++, PERL, Python, .NET framework

Experience in Security provisioning and knowledge of Fuse programming implementation

Drive SLT handler selection for a customized SLT solution

Drive SLT handler enablement by working closely with multiple vendors

Regards

Rohit