Bhargav Ram Kesani

Experienced Analog Layout Engineer with over 6 years in the VLSI industry, specializing in full-custom layout design for analog and mixed-signal integrated circuits across technology nodes from 180nm down to advanced 3nm and 1.8nm (Intel RibbonFET). Proficient in area estimation, floor planning, matched device placement (common-centroid/interdigitated), MIM capacitor integration, and IP-level layout assembly. Adept at collaborating with circuit designers to deliver high-quality, DRC/LVS-clean layouts on schedule.

Skilled in debugging and resolving complex physical verification issues including DRC, LVS, Antenna, Density, and EM/IR. Strong hands-on experience with industry tools such as Cadence Virtuoso, Calibre, ICV, CPDS, and version control systems like Cliosoft and IC Manage. Known for driving layout quality, mentoring team members, and efficiently executing ECOs with minimal design impact.

Designed and taped out analog blocks in 65nm and 180nm technologies, achieving high matching accuracy with common-centroid and interdigitated layout techniques.

• Collaborated with circuit designers to optimize layout for performance and area, ensuring first-pass success with DRC, LVS, and ERC checks using Calibre.
• Independently handled layout of critical analog blocks in 65nm and 28nm for data converter SoCs, mentoring junior layout engineers and interns in layout practices and review procedures.

Mastes in Computer Engineering.

Bachelors in Electronics & Communication Engineering