Logic Design Group Tutor at University of California, Santa Cruz (2025-09 – Present)
- Mentored undergraduates in digital logic design, encompassing Boolean algebra optimization, FSM design, and Verilog implementation, contributing to stronger academic outcomes and comprehension.
- Guided hands-on FPGA development in Xilinx Vivado, helping students move from concept to synthesized, simulation-verified designs.
Residential Assistant at UCSC (2025-09 – Present)
- Served as primary liaison between ~50 residents and university administration, resolving housing issues, coordinating maintenance, and collaborating with cross-functional campus teams.
- Streamlined residential operations by producing onboarding presentations and building budget-tracking spreadsheets for expense management.
Systems Level Test Operator at Nvidia (2024-04 – 2025-11)
- Validated 30–60 Integrated Circuits daily across Blackwell, Hopper, and Tegra architectures, directly supporting production-readiness for Nvidia's next-generation data center and edge platforms.
- Identified systemic failure patterns by correlating test error codes to thermal, electrical, and mechanical root causes; documenting and reporting findings to FA/QA teams, improving yield prediction.
