Hardware Engineer | Electrical Engineer | Verilog
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Recent M.S. Graduate in Electrical & Computer Engineering specializing in RTL design, digital verification, and FPGA development. I have hands-on experience in gate-level simulation with timing, fault injection, and ensuring reliability of digital circuits.
My academic research focused on modeling and mitigating Single Event Transients (SETs) using timing-aware gate-level simulations—skills directly applicable to designing robust, fault-tolerant digital systems.
-HDL Design: Verilog, SystemVerilog, VHDL
-FPGA & ASIC Tools: Xilinx Vivado, ModelSim, Yosys, Icarus Verilog
-Verification: Functional & timing simulation, testbench development, gate-level verification
-Reliability: Fault injection, SET/SEU mitigation, timing-aware fault filtering
-Design Flow: RTL coding, synthesis, place-and-route, timing closure
Key Projects & Achievements:
-Developed a complete RTL-to-gate fault injection framework using open-source tools and the SkyWater 130nm PDK
-Designed and analyzed SET filters to improve digital circuit reliability under radiation exposure
-Synthesized and verified FPGA designs with timing-accurate simulation environments for fault tolerance testing
Passionate about advancing the reliability and performance of digital systems for mission-critical aerospace, defense, and safety-critical applications
Let’s connect if you’re seeking an engineer with strong technical skills, proven research experience, and a drive to deliver robust hardware solutions.
Worked on radiation reliability research focused on modeling and validating digital circuit behavior under fault conditions using gate-level simulations. Developed and executed testbenches in SystemVerilog to inject faults and measure transient responses across various circuit topologies. Performed timing-aware verification of Single Event Transient (SET) filters using synthesized netlists and analyzed power, delay, and fault propagation.
Built and deployed a dynamic simulation framework to support structured data modeling for internal engineering workflows. Designed RESTful APIs to automate simulation data generation, transformation, and storage using Groovy, Grails, and JSON. Developed and tested activity functions to streamline simulation flow and improve data accessibility.
During my Master’s in Electrical and Computer Engineering, I specialized in digital circuit reliability and fault analysis, gaining hands-on experience with gate-level simulation, fault injection, and hardware design using Verilog/SystemVerilog. My thesis focused on modeling Single Event Transients (SETs) and designing SET filters using timing-aware gate-level simulations—a critical area for radiation-hardened electronics in aerospace and safety-critical applications.
I developed a complete fault injection and analysis framework for synthesized circuits, including RTL-to-Gate flow using Yosys and the SkyWater 130nm PDK, and conducted randomized simulations to assess fault impact. I created and analyzed a custom filter that suppressed transient faults, improving overall circuit robustness. This required strong skills in Verilog design, gate-level timing analysis, testbench development, and waveform debugging using tools like GTKWave and Icarus Verilog.
Beyond technical skills, I learned how to manage a long-term research project, communicate technical findings in writing and presentations, and collaborate across tools and environments including Ubuntu, Windows Subsystem for Linux (WSL), and academic EDA tools.
