Rinkal Chauhan

Results-driven GPU Design Engineer specializing in low-power design and PPA optimization across advanced technology nodes. Demonstrated skills in improving dynamic power reduction techniques through deep waveform analysis, and Python based automation for large-scale data sets in GPU architecture.

GPU Logic Design Engineer PPA at Intel Corporation (2022-05 – 2025-08)

• Achieved measured RTL-level dynamic power reductions of approximately 9.5% for EU, 3–3.5% in L2 Caches, and 1.5% in Geometry Shader.
• Supported multicore integrated graphic designs spanning with multiple SKU's execution units, L2 cache banks, and geometry shaders, targeting 1 GHz operating frequency with 0.65–1.0 V across advanced nodes (TSMC 2–4 nm and Intel i14A/i18).
• Optimized XOR-based clock-gating on critical clock paths, improving clock efficiency and contributing to 10-15% improvements in performance – power efficiency.
• Eliminated redundant toggles causing latency in tasks and pipeline stalls, achieving 100 percent compliance with test utilization, and throughput metrics while further reducing power.
• Led RTL-level power analysis and power estimation using Power Artist and Synopsys Prime Time PX, generating block-level power vectors and switching activity statistics.
• Built Python scripts to parse Synopsys PTPX and Ansys Power Artist reports, automating data extraction into Excel based Cdyn rollups.
• Performed deep RTL debug and waveform analysis in Synopsys Verdi to identify power inefficiencies, redundant switching, and performance bottlenecks.
• Collaborated with RTL Design, Verification and architect teams to evaluate and implement power optimization strategies for GPU partitions.

Master of Science in Electrical Engineering – San Jose State University

Bachelor of Technology in Electrical Engineering – L.D.R.P