Electrical and Electronics Engineer
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Electrical and Electronics Engineer with a Master's in Microelectronic Design and hands-on experience in RTL design and functional verification using SystemVerilog and UVM. Skilled in developing coverage-driven verification environments, AXI-based IP verification, SystemVerilog Assertions (SVA), and static timing analysis (STA). Familiar with formal verification methodologies using Cadence JasperGold and experienced in debugging, regression testing, and TCL-based automation within ASIC/SoC design flows.
Master of Science - Electronics and Electrical Engineering - California State University Sacramento (2023-01 - 2025-12)
Bachelor of Science - Electronics and Electrical Engineering - California State University Sacramento (2019-01 - 2023-12)
